R8610 Information
The R8610 is a high performance and fully static 32 bit RISC processor with the compatibility of Windows based, Linux and most popular 32-bit RTOS. It also integrates 16KB write direct map L1 cache, ,Supports LPC/ FWH ( Firmware Hub ) compliant interface, SDRAM / ROM/ memory controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer / counter included) , Fast Ethernet MAC, FIFO UART 10/100M MAC and USB2.0 Host within a single 216 pin LQFP package & 225 balls LFBGA to form a system-on-a-chip (SOC). It provides an ideal solution for the embedded system and communications products (such as thin client, NAT router, home gateway, access point and tablet PC) to bring about desired performance.
The R8610 is a high performance and fully static 32 bit RISC processor with the compatibility of Windows based, Linux and most popular 32-bit RTOS. It also integrates 16KB write direct map L1 cache, ,Supports LPC/ FWH ( Firmware Hub ) compliant interface, SDRAM / ROM/ memory controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer / counter included) , Fast Ethernet MAC, FIFO UART 10/100M MAC and USB2.0 Host within a single 216 pin LQFP package & 225 balls LFBGA to form a system-on-a-chip (SOC). It provides an ideal solution for the embedded system and communications products (such as thin client, NAT router, home gateway, access point and tablet PC) to bring about desired performance.
Specification Form
| Model Number | CPU Archtecture | SDRAM(Type & Capacity) | ROM/Flash(Type & Capacity) | PCI/PCI-E | ISA/LPC | USB/I2C/UART | Ethernet Mac | Package Type |
|---|---|---|---|---|---|---|---|---|
| R8610 | 32 bit, 133Mhz | 16M-Byte | 128-M Byte | PCI X 3 | LPC | USB X 2,UART X 1 | FE X 2 | LQFP216/225LFBGA |
Feature
- Embedded RISC Controller
- Full 32-bit RISC architecture
- Supports diverse operation systems, including Windows based, Linux and most popular 32-bit RTOS
- 6-stage pipeline
- Operation frequency: 133 MHz
- Supports MMU function which includes 32 TLB entries
- MAC Controller
- Supports two-port 10/100 Fast Ethernet MAC
- IEEE 802.3u MII interface
- IEEE 802.3x flow control in full-duplex mode
- Descriptor architecture for packet TX/RX
- Interrupt Controller
- Provides two 8259 compatible interrupt controllers which are cascaded internally
- Independent programmable level/edge-triggered interrupt channels
- Serial IRQ supported
- DMA Controller
- Provides two 8237 DMA compatible controllers which are cascaded internally
- 4 channels for 8-bit DMA transfer and 3 channels for 16-bit transfer
- Two USB 2.0 Host Port Support
- Supports HS, FS and LS
- FIFO UART Port
- A high performance UART port with transmit and receive FIFOs
- Supports the programmable baud rate generator with the data rates from 50 to 115,200 bps
- The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits
- PCI Control Interface
- Supports PCI Rev 2.1 specification
- 32-bit bus interface
- Supports PCI clock at 33 MHz
- Supports PCI host
- Supports PCI master/slave
- Up to 133 Mbytes/sec maximum bandwidth
- Supports up to 3 external master devices on PCI
- Provides four PCI interrupt channels
- LPC (Low Pin Count) Bus Interface
- LPC revision 1.0 compliant
- Supports LPC/FWH (Firmware Hub) compliant interfaces
- Provides the interface to connect an LPC/FWH Flash ROM or Super I/O chip
- Supports LPC DMA
- Supports serial IRQ
- Supports bus master request in DMA channel 4
- Supports 8/16/32-bit transfer size
- X-Bus Interface
- Provides the interface to boot ROM BIOS & DOC (Disk On Chip).
- Supports 8/16-bit data width
- Provides ROMCS_n for booting from X-bus Flash ROM
- Supports from 64K-byte to Max. 16M-byte ROM space addressing
- Supports two independent and programmable CSs (Chip Selects)
- SDRAM Control Interface
- PC100/PC133 compliant
- Supports 16-bit data bus width
- Supports speeds up to 133 MHz and above
- Supports maximum 128 MB memory space
- On-Chip L1 16KB Cache
- Unifies instructions and data cache
- Supports write through for cache write policy
- Snooping mechanism support for data coherence between main memory and cache
- Direct map
- General Programmable I/O
- Supports 58 programmable I/O pins
- Each GPIO pin can be individually configured to be an input/output pin
- Counter/Timers
- 8254 compatible timers
- Provides three independent programmable timers / counters
- Supports a watchdog timer (WDT)
- Supports a speaker output
- Real Time Clock (External)
- Provides a direct interface to external RTC chips